The present disclosure relates in general to semiconductor devices and their manufacture, and more specifically to controlling the height of a dielectric region of a fin-type field effect transistor (FinFET) during fabrication thereof.
Typical semiconductor devices are formed using active regions of a wafer. The active regions are defined by isolation regions used to separate and electrically isolate adjacent semiconductor devices. For example, in an integrated circuit having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.
One particularly advantageous type of MOSFET is known generally as a fin-type field effect transistor (FinFET), an example of which is shown in FIG. 1 as a three-dimensional view of a FinFET 100. The basic electrical layout and mode of operation of FinFET 100 do not differ significantly from a traditional field effect transistor. FinFET 100 includes a semiconductor substrate 102, a shallow trench isolation (STI) layer 104, a fin 106 and a gate 114, configured and arranged as shown. Fin 106 includes a source region 108, a drain region 110 and a channel region 112, wherein gate 114 extends over the top and sides of channel region 112. For ease of illustration, a single fin is shown in FIG. 1. In practice, FinFET devices are fabricated having multiple fins formed on STI 104 and substrate 102. Substrate 102 may be silicon, STI 104 may be an oxide (e.g., SiO2) and fin 106 may be silicon that has been enriched to a desired concentration level of germanium. Gate 114 controls the source to drain current flow (labeled ELECTRICITY FLOW in FIG. 1). In contrast to planar MOSFETs, however, source 108, drain 110 and channel 112 are built as a three-dimensional bar on top of STI layer 104 and semiconductor substrate 102. The three-dimensional bar is the aforementioned “fin 106,” which serves as the body of the device. The gate electrode is then wrapped over the top and sides of the fin, and the portion of the fin that is under the gate electrode functions as the channel. The source and drain regions are the portions of the fin on either side of the channel that are not under the gate electrode. The dimensions of the fin establish the effective channel length for the transistor.
It is a challenge in FinFET manufacturing processes to form fins with uniform heights and widths. An “effective” dimension of a FinFET is usually different from the dimension that is selected during the device layout stage. This is because different fabrication processes inevitably results in some dimension offset during the manufacturing process. For example, effective channel width control in bulk FinFET is challenging because the excess reactive ion etching (RIE) and wet etching processes that must be applied can cause severe STI depth variation. Outside of the gate, both stack etching and spacer pull down processes can result in STI recess, while an epitaxial (epi) layer pre-clean process can lead to oxide loss. The subsequent fin recess operations for in-situ doped epi extension drive-in cause junction depth variation. For structures underneath the gate, the STI loss mainly comes from poly RIE and wet etch processes for accomplishing poly pull and molecular layer deposition (MLD) oxide removal. The application of a high-K (HK) pre-clean stage can result in additional oxide etching. Because the effective width (WEFF) is defined as the gate to fin overlap region, these etch processes result in WEFF variation.